Bandwidth spreading by direct modulation of signals by
a wideband spread signal (also called code) is called direct
sequence spread spectrum (DS SS). The DSSS signal is then
modulated by a carrier before final transmission. In DSSS,
the base band signals are usually called bits, and the code
bits are called chips. Typically, the baseband signal bandwidth
is multiplies several times by the spreading signals. In
other words, the chip rate is much higher than the bit rate.
The spreading signal sequence is unique for a transmitter,
and the same chip sequence is used at the receiver to re-construct
the signals (data bits). A mechanism, by name correlation
is used to synchronize the received spread signals (that
contain data) with the locally generated code. At maximum
received signal strength, correlation said to have occurred.
The receiver then enters the tracking mode, such that the
spread signal modulated signals are received without interruption.
A simple DSSS system is described below:
d(t) is the input data bits
c(t) is the code bits
x(t) is the frequency converted signal, ready for transmission.
A note about why frequency up conversion is required for
radio transmission: Base band, and very low frequencies are
susceptible to heavy attenuation during transmission. In addition,
imagine every transmitter transmitting in the base band frequencies.
It is practically impossible for everyone to transmit in base
band frequencies (A base band frequency is the frequency spectrum
that is occupied by the unmodulated signals). Hence up-conversion
of frequency is normally done to comply with the transmission
In the DSSS transmitter, a code generator is a pseudo random
generator that generates a known pseudo noise code sequence.
Normally, the code has finite length (say 1024 chips), and repeats
periodically. The requirements for a good PN code is discussed
in a later section.
An XOR gate can be used for spreading the data bits. The
input, code, and the resulting output are displayed in the figure
In the figure shown above, each data bit is coded with 8
chips. In practice, this would be much higher, of the order
of 1024 or even more. Higher the number of chips per bit, higher
will be the processing gain. Processing gain is defined below:
Processing Gain: One important parameter of DS SS receiver
is the processing gain. Consider a data rate of 10KBPS, and
Chip rate of 1MBPS. The processing gain is given by 10 log [rc/rb],
where rc is the chip rate, and rb is the data rate. For a chip
rate of 1MBPS, and a data rate of 1KBPS, the processing gain
is 10log or 30dB. The processing gain is a measure of
immunity to noise, and jamming signals. Higher the processing
gain, more the band spread of the signals.
Higher processing gain results in greater immunity to noise,
and interfering signals.
After spreading, the signals are unconverted and transmitted.
A simplified DS SS receiver block diagram is shown below.
It consists of a PN generator that feeds the matching chip
sequence to an XOR gate to reproduce the original bit sequence.
The PN generator is driven by an error signal from the output
of the LPF, so that chip timing is adjusted to produce maximum
signal threshold. Normally, the acquisition of the data is done
through a two step process. The first is acquisition, and the
second is tracking. Acquisition refers to acquiring the chip
timing of the received signals. This may further be sub-divided
into course acquisition, and fine acquisition. The two are differentiated
by the amount of chip timing adjustment. Once the acquisition
is achieved, then the received signals must be tracked properly.
Otherwise, you may loose the lock, resulting in loss of data
bits. As with conventional receiver operation, an error voltage
at the output of the LPF (or an Integrator) provides necessary
correction to the PN Generator.
Codes (PN Codes)The PN codes used for DSSS require
certain mathematical properties
1. Maximum Length Sequences: These are PN sequences that
repeat every 2n -1, where n is an integer. These
sequences can be implemented using shift registers. The PN sequences
must exhibit good correlation properties. Two such sequences
are Barker Codes, and Willard Codes.
2. Maximum Auto-Correlation: When the received signal is
mixed with locally generated PN sequence, it must result in
maximum signal strength at the point of synchronization.
3. Minimum Cross-Correlation: When the received signal with
a different PN sequence than that of the receiver, is mixed
with the locally generated PN sequence, it must result in minimum
signal strength. This would enable a DSSS receiver to receive
only the signal matching the PN code. This property is known
as Orthogonality of PN Sequences.
b. Frequency Hopping (FH) SS Systems
Here the transmitted signal appears as a data modulated carrier
which is hopping from one frequency to next, and therefore,
it is called frequency hopping spread spectrum (FH-SS). FH systems
work by driving a frequency synthesizer with pseudorandom sequence
of numbers that result in the synthesizer hopping different
frequencies at different points, and thus achieving signal spread.
At the receiver end, the same principle works. A synthesizer
is driven by a matching code to achieve maximum threshold detection
of received signals.
A simplified block schematic of a FH SS system is shown below:
The transmitter consists of a baseband modulator followed
by frequency synthesizer. The frequency synthesizer is driven
by a PN generator. A PN generator may be built internal to the
A FH-SS receiver consists of a down converter followed by
a demodulator. A synthesizer, driven by a matching PN generator
is used to down convert the received signals. A miximum received
signal threshold signifies locking.
Time Hopping (TH) SS Systems
Time hopping is not used as frequency as DSSS and FHSS. Time
Hopping to spread the carrier is achieved by randomly spacing
narrow transmitted pulses.
d. Recovery of Spread Spectrum Signals: Important Timing Signals
In all cases of SS receivers, faithful recovery of the transmitted
signals require the following:
a. Correlation Interval Synchronization: Receiving bits is
achieved by proper correlator (or integrator) timing. Proper
start/stop times for correlator are required for minimizing
the received bit errors.
b. SS Generator Synchronization: Timing signals are required
to control the SS wave form generator signals. Direct Sequence
systems employ a clock ticking at the chip rate 1/tc,
and FH systems have a clock operating at the hopping rate 1/th.
c. Carrier Synchronization: Faithful reproduction of the
transmitted signals to baseband requires down-conversion, and
demodulation. This can be achieved only if the locally generated
frequency and phase are in sync with the received carrier frequency.